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gs8162z72cc-333/300/250/200/150 18mb pipelined and flow through synchronous nbt sram 333 mhz ? 150 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 209-bump bga commercial temp industrial temp preliminary rev: 1.01d 2/2011 1/28 ? 2004, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? 2.5 v or 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? user-configurable pipeline and flow through mode ? zq mode pin for user-selectable high /low output drive ? ieee 1149.1 jtag-compatible boundary scan ? lbo pin for linear or interleave burst mode ? pin-compatible with 2m, 4m, and 8m devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? zz pin for automatic power-down ? jedec-standard 209- bump bga package ? rohs-compliant 209-bump bga package available functional description the gs8162z72cc is an 18mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched fr om read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. burst order control ( lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and output enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's out put drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs8162z72cc may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. the gs8162z72cc is implemented with gsi's high perform ance cmos technology and is available in a jedec- standard 209-bump bga package. parameter synopsis -333 -300 -250 -200 -150 unit pipeline 3-1-1-1 t kq tcycle 2.8 3.0 2.8 3.3 3.0 4.0 3.0 5.0 3.8 6.7 ns ns curr 545 495 425 345 270 ma flow through 2-1-1-1 t kq tcycle 4.5 4.5 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns curr 380 345 315 275 250 ma
gs8162z72 pad out?209-bump bga ? top view (package c) 1 2 3 4 5 6 7 8 9 10 11 a dqg dqg a e2 a adv a e 3 a dqb dqb b dqg dqg b c b g nc w a b b b f dqb dqb c dqg dqg b h b d nc e 1 nc b e b a dqb dqb d dqg dqg v ss nc nc g nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss mcl v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf k nc nc ck nc v ss cke v ss nc nc nc nc l dqh dqh v ddq v ddq v dd ft v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc lbo nc nc v ss dqe dqe u dqd dqd nc a nc a nc a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe rev 10 11 x 19 bump bga ? 14 x 22 mm 2 body ? 1 mm bump pitch gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 2/28 ? 2004, gsi technology
gs8162z72 209-bump bg a pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d dq e dq f dq g dq h i/o data input and output pins b a , b b , b c , b d, b e , b f , b g , b h i byte write enable for dq a , dq b , dq c , dq d, dq e , dq f , dq g , dq h i/os; active low nc ? no connect ck i clock input signal; active high w i write enable. writes all enabled bytes; active low e 1, e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active high zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low mch i must connect high mcl must connect low cke i clock enable; active low bw i byte enable; active low zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 3/28 ? 2004, gsi technology
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 4/28 ? 2004, gsi technology functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operat ions must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs ( e 1 , e 2, and e 3 ). deassertion of an y one of the enable inputs will deactivate the device. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables ( e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register an d presented to the memory co re and control logic. the co ntrol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is asserted low, and the write input is sampled low at the rising edge of clock. the byte write enable inputs ( b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching the write command versus data pipe line length (2 cycles) to the read comman d versus data pipeline length (2 cycles). a t the first rising edge of clock, enable, writ e, byte write(s), and address are registered . the data in associated with that addr ess is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to op erati ons in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in th at the write pipeline is one cy cle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second risin g edge of clock.
synchronous truth table operation type address ck cke adv w bx e 1 e 2 e 3 g zz dq notes read cycle, begin burst r external l-h l l h x l h l l l q read cycle, continue burst b next l-h l h x x x x x l l q 1,10 nop/read, begin burst r external l-h l l h x l h l h l high-z 2 dummy read, continue burst b next l-h l h x x x x x h l high-z 1,2,10 write cycle, begin burst w external l-h l l l l l h l x l d 3 write abort, begin burst d none l-h l l l h l h l x l high-z 1 write cycle, continue burst b next l-h l h x l x x x x l d 1,3,10 write abort, continue burst b next l-h l h x h x x x x l high-z 1,2,3,10 deselect cycle, power down d none l-h l l x x h x x x l high-z deselect cycle, power down d none l-h l l x x x x h x l high-z deselect cycle, power down d none l-h l l x x x l x x l high-z deselect cycle, continue d none l-h l h x x x x x x l high-z 1 sleep mode none x x x x x x x x x h high-z clock edge ignore, stall current l-h h x x x x x x x l - 4 notes: 1. continue burst cycles, whether read or wr ite, use the same control inputs. a deselect continue cycle can only be entered into if a deselect cycle is executed first. 2. dummy read and write abort can be consider ed nops because the sra m performs no oper ation. a write abort occurs when the w pin is sampled low but no byte write pins are ac tive so no write operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off during write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensures all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles. gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 5/28 ? 2004, gsi technology
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 6/28 ? 2004, gsi technology deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in t he synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipelined and flow th rough read/write co ntrol state diagram w r pipelined and flow through r ead write contro l state diagram
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 7/28 ? 2004, gsi technology intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state pipeline mode da ta i/o state diagram
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 8/28 ? 2004, gsi technology high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipeline and flow th rough read write c ontrol state diagram flow through mode data i/o state diagram
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 9/28 ? 2004, gsi technology burst cycles although nbt rams are designed to sustain 100% bus bandwidth by elim inating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded into the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after fo ur addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst se quence is selected. see the tab les below for details. flxdrive? the zq pin allows selection between nbt ram nominal drive strength (zq low) for multi-drop bus applications and low drive stren gth (zq floating or high) point-to-point applications . see the output driver char acteristics chart for details. mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb flxdrive output impedance control zq l high drive (low impedance) h or nc low drive (high impedance) note: there are pull-up devices on the zq and ft pins and a pull-down device on t he zz pin, so those input pi ns can be unconnected and the chip will operate in the default states as specified in the above tables.
note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 10/28 ? 2004, gsi technology burst counter sequences bpr 1999.05.18 sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exitin g sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram tzzr tzzh tzzs tkltkl tkhtkh tkctkc ck zz designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on bump 5r. not all vendors offer this option, however most mark bump 5r as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets.
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0 .5 to 4.6 v v ddq voltage in v ddq pins ? 0 .5 to 4.6 v v i/o voltage on i/o pins ? 0 .5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 11/28 ? 2004, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceede d. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. power supply voltage ranges parameter symbol min. typ. max. unit 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v v dd3 range logic levels parameter symbol min. typ. max. unit input high voltage v ih 2.0 ? v dd + 0.3 v input low voltage v il ? 0.3 ? 0.8 v note: v ihq (max) is voltage on v ddq pins plus 0.3 v.
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 12/28 ? 2004, gsi technology v dd2 range logic levels parameter symbol min. typ. max. unit input high voltage v ih 0.6*v dd ? v dd + 0.3 v input low voltage v il ? 0.3 ? 0.3*v dd v note: v ihq (max) is voltage on v ddq pins plus 0.3 v. recommended operating temperatures parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions)* t a ? 40 25 85 c note: * the part numbers of industrial temper ature range versions end with the character ?i?. unless otherwise noted, all performan ce specifications quoted are evaluated for worst case in the temperature range marked on the device. thermal impedance package test pcb substrate ja (c/w) airflow = 0 m/s ja (c/w) airflow = 1 m/s ja (c/w) airflow = 2 m/s jb (c/w) jc (c/w) 209 bga 4-layer 15.6 12.6 11.7 5.6 2.5 notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature. 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkc v dd + 2.0 v 50% v dd v il note: input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
capacitance o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 13/28 ? 2004, gsi technology note: these parameters are sample tested. ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as sho wn in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dq v ddq/2 50 30pf * output load 1 * distributed test jig capacitance (t a = 25
dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 u a 1 ua 100 ua ft , zq input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 u a 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 14/28 ? 2004, gsi technology
operating currents parameter test conditions mode symbol -333 -300 -250 -200 -150 unit 0 to 70c ? 40 to 85c 0 to c ? 40 to 85 c 0 to 70 c ? 40 to 85 c 0 to c ? 40 to 85c 0 to 70 c ? 40 to 85 c operating current device selected; all other inputs v ih or v il output open (x72) pipeline i dd i ddq 460 85 470 85 415 80 425 80 350 75 360 75 290 55 300 55 230 40 240 40 ma flow th rough i dd i ddq 320 60 330 60 290 55 300 55 265 50 275 50 230 45 240 45 210 40 220 40 ma standby current zz v dd ? 0.2 v ? pipeline i sb 40 50 40 50 40 50 40 50 40 50 ma flow th rough i sb 40 50 40 50 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 85 90 85 90 85 90 85 90 85 90 ma flow th rough i dd 60 65 60 65 60 65 50 55 50 55 ma gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 15/28 ? 2004, gsi technology notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario.
ac electrical characteristics parameter symbol -333 -300 -250 -200 -150 unit min max min max min max min max min max pipeline clock cycle time tkc 3.0 ? 3.3 ? 4.0 ? 5.0 ? 6.7 ? ns clock to output valid tkq ? 2.8 ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.0 ? 1.0 ? 1.2 ? 1.5 ? 1.5 ? ns hold time th 0.1 ? 0.1 ? 0.2 ? 0.4 ? 0.5 ? ns flow through clock cycle time tkc 4.5 ? 5.0 ? 5.5 ? 6.5 ? 7.5 ? ns clock to output valid tkq ? 4.5 ? 5.0 ? 5.5 ? 6.5 ? 7.5 ns clock to output invalid tkqx 2.0 ? 2.0 ? 2.0 ? ? 6.5 ? 7.5 ns clock to output in low-z tlz 1 2.0 ? 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns setup time ts 1.3 ? 1.4 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.3 ? 0.4 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.0 ? 1.0 ? 1.3 ? 1.3 ? 1.5 ? ns clock low time tkl 1.2 ? 1.2 ? 1.5 ? 1.5 ? 1.7 ? ns clock to output in high -z thz 1 1.5 2.8 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 ns g to output valid toe ? 2.8 ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 2.8 ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? 20 ? ns gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 16/28 ? 2004, gsi technology notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup a nd hold times as specified above.
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 17/28 ? 2004, gsi technology pipeline mode timing (nbt) write a read b suspend read c write d write no-op read e deselect thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts th ts tkctkc tkltkl tkhtkh ab cd e d(a) d(d) q(e) q(b) q(c) ck a cke e * adv w bn dq
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 18/28 ? 2004, gsi technology flow through mode timing (nbt) write a write b write b+1 read c cont read d write e read f write g d(a) d(b) d(b+1) q(c) q(d) d(e) q(f) d(g) tolz toe tohz tkqx tkq tlz thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts tkctkc tkltkl tkhtkh ab c defg *note: e = high(false) if e1 = 1 or e2 = 0 or e3 = 1 ck cke e adv w bn a0?an dq g
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 19/28 ? 2004, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is t he command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers pla ced between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state o f the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as tes t access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible.
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 20/28 ? 2004, gsi technology boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pin s. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller m* 1 0 control signals * for the value of m, see the bsdl file, which is av ailable at by contacting us at apps@gsitechnology.com . jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins.
id register contents not used gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1 gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 21/28 ? 2004, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be us ed to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction register are loaded wit h 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instructions only wh en the controller is moved to update-ir state. the tap instruction set for this devic e is listed in the following table.
select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 22/28 ? 2004, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in stru ction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins.
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 23/28 ? 2004, gsi technology typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the defau lt values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id registe r when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the ins truction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r fu ture use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister betwe en tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ p reload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
jtag port recommended operat ing conditions and dc characteristics (2 .5/3.3 v version) parameter symbol min. max. unit notes 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v 1 2.5 v test port input low voltage v ilj2 ?0.3 0.3 * v dd2 v 1 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v 1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v < v i < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 24/28 ? 2004, gsi technology notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 30pf * jtag port ac test load * distributed test jig capacitance
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 25/28 ? 2004, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com .
gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 26/28 ? 2004, gsi technology package dimensions? 209-bump bga (package c) 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array c 11 10 9 8 7 6 5 4 3 2 1 bottom view ?0.10 ?0.30 c c a b m m ?0.50~0.70 (209x) a b c d e f g h j k l m n p r t u v w 1.0 1.0 18.0 22.0 b 14.0 a 0.20(4x) 1.0 1.0 10.0 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k l m n p r t u v w a1 corner top view seating plane 0.15 c 0.40~0.60 1.70 max.
ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 256k x 72 gs8162z72cc-333 nbt pipeline/flow through 209 bga 333/4.5 c 256k x 72 gs8162z72cc-300 nbt pipeline/flow through 209 bga 300/5 c 256k x 72 gs8162z72cc-250 nbt pipeline/flow through 209 bga 250/5.5 c 256k x 72 gs8162z72cc-200 nbt pipeline/flow through 209 bga 200/6.5 c 256k x 72 gs8162z72cc-150 nbt pipeline/flow through 209 bga 150/7.5 c 256k x 72 gs8162z72cc-333i nbt pipeline/flow through 209 bga 333/4.5 i 256k x 72 gs8162z72cc-30i nbt pipeline/flow through 209 bga 300/5 i 256k x 72 gs8162z72cc-250i nbt pipeline/flow through 209 bga 250/5.5 i 256k x 72 gs8162z72cc-200i nbt pipeline/flow through 209 bga 200/6.5 i 256k x 72 gs8162z72cc-150i nbt pipeline/flow through 209 bga 150/7.5 i 256k x 72 gs8162z72cgc-333 nbt pipeline/flow through rohs-compliant 209 bga 333/4.5 c 256k x 72 gs8162z72cgc-300 nbt pipeline/flow through rohs-compliant 209 bga 300/5 c 256k x 72 gs8162z72cgc-250 nbt pipeline/flow through rohs-compliant 209 bga 250/5.5 c 256k x 72 gs8162z72cgc-200 nbt pipeline/flow through rohs-compliant 209 bga 200/6.5 c 256k x 72 gs8162z72cgc-150 nbt pipeline/flow through rohs-compliant 209 bga 150/7.5 c 256k x 72 gs8162z72cgc-333i nbt pipeline/flow through rohs-compliant 209 bga 333/4.5 i 256k x 72 gs8162z72cgc-300i nbt pipeline/flow through rohs-compliant 209 bga 300/5 i 256k x 72 gs8162z72cgc-250i nbt pipeline/flow through rohs-compliant 209 bga 250/5.5 i 256k x 72 gs8162z72cgc-200i nbt pipeline/flow through rohs-compliant 209 bga 200/6.5 i 256k x 72 gs8162z72cgc-150i nbt pipeline/flow through rohs-compliant 209 bga 150/7.5 i notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs8162z72c c-250it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. c = commercial temperature range. i = industrial t emperature range. 4. gsi offers other versions this type of device in many differ ent configurat ions and with a variety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 27/28 ? 2004, gsi technology
18mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason gs8162zxxc_r1 ? creation of new datasheet 8162zxxc_r1; 8 162zxxc_r1_01 content ? added 200 & 150 mhz speed bins ? added pb-free information ? rev1.01a: updated coplanarity for 209 bga mechanical, cor - rected error in ordering information table, updated synchro - nous truth table (pg. 5) ? rev1.01b: corrected bga pin description heading ? rev1.01c: removed on-chip parity references. ? rev1.01d: corrected mode pins table; added thermal info gs8162z72cc-333/300/250/200/150 preliminary specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01d 2/2011 28/28 ? 2004, gsi technology

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